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| TH71102 315/433MHz FSK/FM/ASK Receiver Features ! ! ! ! ! ! ! Double superhet architecture for high degree of image rejection FSK for digital data and FM reception for analog signal transmission FM/FSK demodulation with phase-coincidence demodulator Low current consumption in active mode and very low standby current Switchable LNA gain for improved dynamic range RSSI allows signal strength indication and ASK detection Surface mount package LQFP32 Ordering Information Part No. TH71102 Temperature Range -40 C to 85C Package LQFP32 Application Examples ! ! ! ! ! General digital and analog 315 MHz or 433 MHz ISM band usage Low-power telemetry Alarm and security systems Keyless car and central locking Pagers Technical Data Overview ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! Input frequency range: 300 MHz to 450 MHz Power supply range: 2.5 V to 5.5 V Temperature range: -40 C to +85 C Operating current: 6.5 mA at low gain and 8.2 mA at high gain mode Standby current: < 100 nA 1) with 40 kHz second IF filter BW (incl. SAW front-end filter loss) Sensitivity: -111 dBm 2) Sensitivity: -104 dBm with 150 kHz second IF filter BW (incl. SAW front-end filter loss) Range of first IF: 10 MHz to 80 MHz Range of second IF: 455 kHz to 21.4 MHz Maximum input level: -10 dBm at ASK and 0 dBm at FSK nd Image rejection: > 65 dB (e.g. with SAW front-end filter and at 10.7 MHz 2 IF) Spurious emission: < -70 dBm Input frequency acceptance: 50 kHz (with AFC option) RSSI range: 70 dB Frequency deviation range: 5 kHz to 120 kHz Maximum data rate: 80 kbit/s NRZ Maximum analog modulation frequency: 15 kHz 1) 2) at 8 kHz FSK deviation, BER = 310 and phase-coincidence demodulation -3 at 50 kHz FSK deviation, BER = 310 and phase-coincidence demodulation -3 TH71102 Data Sheet 3901071102 Page 1 of 20 Nov. 2001 Rev. 005 TH71102 315/433MHz FSK/FM/ASK Receiver General Description The TH71102 receiver IC consists of the following building blocks: " " " " " " " " " PLL synthesizer (PLL SYNTH) for generation of the first and second local oscillator signals LO1 and LO2 Parts of the PLL SYNTH are the high-frequency VCO1, the feedback dividers DIV_8 and DIV_2, a phase-frequency detector (PFD) with charge pump (CP) and a crystal-based reference oscillator (RO) Low-noise amplifier (LNA) for high-sensitivity RF signal reception First mixer (MIX1) for down-conversion of the RF signal to the first IF (IF1) second mixer (MIX2) for down-conversion of the IF1 to the second IF (IF2) IF amplifier (IFA) to amplify and limit the IF2 signal and for RSSI generation Phase coincidence demodulator (DEMOD) with third mixer (MIX3) to demodulate the IF signal Operational amplifier (OA) for data slicing, filtering and ASK detection Bias circuitry for bandgap biasing and circuit shutdown With the TH71102 receiver chip, various circuit configurations can be arranged in order to meet a number of different customer requirements. For FM/FSK reception the IF tank used in the phase coincidence demodulator can be constituted either by a ceramic resonator or an LC tank (optionally with a varactor diode to create an AFC circuit). In ASK configuration, the RSSI signal is feed to an ASK detector, which is constituted by the operational amplifier. Demodulation FM / FSK FM / FSK ASK Type of receiver narrow-band RX with ceramic demodulation tank wide-band RX with LC demodulation tank RX with RSSI-based demodulation The superheterodyne configuration is double conversion where MIX1 and MIX2 are driven by the internal local oscillator signals LO1 and LO2, respectively. This allows a high degree of image rejection, achieved in conjunction with an RF frontend filter. Efficient RF frontend filtering is realized by using a SAW, ceramic or helix filter in front of the LNA and by adding an LC filter at the LNA output. A single-conversion variant, called TH71101, is also available. Both RXICs have the same die. At the TH71101 the second mixer MIX2 operates as an amplifier. TH71102 Data Sheet 3901071102 Page 2 of 20 Nov. 2001 Rev. 005 TH71102 315/433MHz FSK/FM/ASK Receiver Block Diagram OUTP OUTN OAN OAP 23 24 20 OA OUT_OA 19 18 VCC_BIAS VEE_BIAS MIX3 IN_DEM 16 22 17 BIAS ENRX 28 OUT_IFA 15 VCC_PLL 14 21 IFA 13 FBC1 12 VEE_IF 10 CP OUT_MIX2 9 IF2 PFD IN_IFA 11 DIV_2 LO2 VCC_MIX 8 IF1N 7 MIX2 DIV_8 IF1P 6 IF1 IN_MIX1 4 OUT_LNA 3 MIX1 VEE_MIX 5 LO1 VCO1 VEE_LNA LNA GAIN_LNA 2 VCC_LNA 32 IN_LNA VEE_LNAC 1 Fig. 1: TH71102 block diagram TH71102 Data Sheet 3901071102 31 Page 3 of 20 30 29 LF 26 RO FPC2 RO 25 RSSI VEE_RO 27 Nov. 2001 Rev. 005 TH71102 315/433MHz FSK/FM/ASK Receiver Frequency Planning Frequency planning is straightforward for single-conversion applications because there is only one IF that might be chosen, and then the only possible choice is low-side or high-side injection of the LO1 signal (which is now the one and only LO signal in the receiver). The receiver's double-conversion architecture requires careful frequency planning. Besides the desired RF input signal, there are a number of spurious signals that may cause an undesired response at the output. Among them are the image of the RF signal (that must be suppressed by the RF front-end filter), spurious signals injected to the first IF (IF1) and their images which could be mixed down to the same second IF (IF2) as the desired RF signal (they must be suppressed by the LC filter at IF1 and/or by low-crosstalk design). By configuring the TH71102 for double conversion and using its internal PLL synthesizer with fixed feedback divider ratios of N1 = 8 (DIV_8) and N2 = 2 (DIV_2), four types of down-conversion are possible: low-side injection of LO1 and LO2 (low-low), LO1 low-side and LO2 high-side (low-high), LO1 high-side and LO2 low-side (high-low) or LO1 and LO2 high-side (high-high). The following table summarizes some equations that are useful to calculate the crystal reference frequency (REF), the first IF (IF1) and the VCO1 or first LO frequency (LO1), respectively, for a given RF and second IF (IF2). Injection type REF LO1 IF1 LO2 IF2 high-high (RF - IF2)/14 16*REF LO1 - RF 2*REF LO2 - IF1 low-low (RF - IF2)/18 16*REF RF - LO1 2*REF IF1 - LO2 high-low (RF + IF2)/14 16*REF LO1 - RF 2*REF IF1 - LO2 low-high (RF + IF2)/18 16*REF RF - LO1 2*REF LO2 - IF1 The following table depicts generated, desired, possible images and some undesired signals considering the examples of 315 MHz and 433.6 MHz RF reception at IF2 = 10.7 MHz. Signal type Injection type REF / MHz LO1 / MHz IF1 / MHz LO2 / MHz RF = 315 MHz high-high 21.73571 RF = 315 MHz low-low 16.90556 RF = 315 MHz high-low 23.26429 RF = 315 MHz low-high 18.09444 RF = RF = RF = RF = 433.6 MHz 433.6 MHz 433.6 MHz 433.6 MHz high-high 30.20714 low-low 23.49444 high-low 31.73571 low-high 24.68333 347.77143 270.48889 372.22857 32.77143 43.47143 44.51111 33.81111 57.22857 46.52857 289.51111 483.31429 375.91111 507.77143 394.93333 25.48889 36.18889 49.71429 60.41429 57.68889 46.98889 74.17143 63.47143 38.66667 49.36667 RF image/MHz 380.54286 225.97778 429.45714 IF1 image/MHz 54.17143 23.11111 35.82857 264.02222 533.02857 318.22222 581.94286 356.26667 46.88889 71.11429 36.28889 52.77143 60.06667 The selection of the reference crystal frequency is based on some assumptions. As for example: the first IF and the image frequencies should not be in a radio band where strong interfering signals might occur (because they could represent parasitic receiving signals), the LO1 signal should be in the range of 300 MHz to 430 MHz (because this is the optimum frequency range of the VCO1). Furthermore the first IF should be as high as possible to achieve highest RF image rejection. The columns in bold depict the selected frequency plans to receive at 315 MHz and 433.6 MHz, respectively. TH71102 Data Sheet 3901071102 Page 4 of 20 Nov. 2001 Rev. 005 TH71102 315/433MHz FSK/FM/ASK Receiver Pin Definition and Description Pin No. 3 Name OUT_LNA I/O Type analog output analog input ground 5k Functional Schematic OUT_LNA 3 Description LNA open-collector output, to be connected to external LC tank that resonates at RF LNA input, approx. 26 single-ended 31 IN_LNA IN_LNA 31 VEE_LNAC 1 VEE_LNAC 1 ground of LNA core (cascode) LNA gain control (CMOS input with hysteresis) 2 GAIN_LNA analog input GAIN_LNA 2 400 4 IN_MIX1 analog input IN_MIX1 4 13 MIX1 input, approx. 33 single-ended 13 500A 5 6 VEE_MIX IF1P ground analog I/O IF1P 6 20p VCC 20p LNA biasing ground open-collector output, to be connected to external LC tank that resonates at first IF open-collector output, to be connected to external LC tank that resonates at first IF VEE IF1N 7 7 IF1N analog I/O 2x500A VEE 8 9 VCC_MIX OUT_MIX2 supply analog output OUT_MIX2 9 230A 130 MIX1 and MIX2 positive supply 6.8k MIX2 output, approx. 330 output impedance 10 VEE_IF ground ground for MIX2, IFA and DEMOD TH71102 Data Sheet 3901071102 Page 5 of 20 Nov. 2001 Rev. 005 TH71102 315/433MHz FSK/FM/ASK Receiver Pin No. 11 Name IN_IFA I/O Type analog input IN_IFA 11 VEE VCC Functional Schematic VCC VCC Description IFA input, approx. 2.2k input impedance FBC1 12 12 FBC1 analog I/O 2.2k 2.2k 200A VEE to be connected to external IFA feedback capacitor 13 FBC2 analog I/O FBC2 13 VEE VEE to be connected to external IFA feedback capacitor 14 15 VCC_IF OUT_IFA supply analog I/O OUT_IFA 15 40A positive supply for IFA, DEMOD IFA output and MIX3 input (of DEMOD) 16 IN_DEM analog input IN_DEM 16 DEMOD input, to MIX3 core 47k 17 18 VCC_BIAS OUT_OA supply analog output OUT_OA 18 50 positive supply of general bias system and OA OA output, 40uA current drive capability 19 OAN analog input OAN 50 20A 50 20 OAP analog input 19 negative OA input, input voltage limited to approx. 0.7 Vpp between pins OAP and OAN OAP negative OA input, input 20 voltage limited to approx. 0.7 Vpp between pins OAP and OAN TH71102 Data Sheet 3901071102 Page 6 of 20 Nov. 2001 Rev. 005 TH71102 315/433MHz FSK/FM/ASK Receiver Pin No. 21 Name RSSI I/O Type analog output Functional Schematic Description RSSI output, for RSSI and ASK detection, approx. 36k output impedance RSSI 21 I (Pi) 50 36k 22 23 VEE_BIAS OUTP ground analog output analog ground for general bias system and OA OUTP OUTN 23 24 50 FSK/FM positive output, output impedance of 100k to 300k 20A 20A 24 OUTN FSK/FM negative output, output impedance of 100k to 300k ground of dividers, PFD and RO RO input, Colpitts type oscillator with internal feedback capacitors 25 26 VEE_RO RO ground analog input RO 26 30p 50k 30p 27 28 VCC_PLL ENRX supply digital input ENRX 28 1.5k positive supply of RO, DIV, PFD and charge pump mode control input (CMOS Input) 29 LF analog output LF 29 400 200 charge pump output and VCO1 control input 4p 30 32 VEE_LNA VCC_LNA ground supply LNA biasing ground positive supply of LNA biasing TH71102 Data Sheet 3901071102 Page 7 of 20 Nov. 2001 Rev. 005 TH71102 315/433MHz FSK/FM/ASK Receiver Technical Data Mode Configurations ENRX Mode standby mode entire chip active Description 0 SBY 1 ON Note: ENRX are pulled down internally LNA Gain Control VGAIN_LNA < 0.8 V > 1.4 V Mode HIGH GAIN LOW GAIN Description LNA set to high gain by voltage at GAIN_LNA LNA set to low gain by voltage at GAIN_LNA Note: hysteresis between gain modes to ensure stability Absolute Maximum Ratings Parameter Supply voltage Input voltage Input RF level Storage temperature Electrostatic discharge Symbol Vcc VIN Pimax TSTG ESD Condition / Note Min 0 - 0.3 no damage -40 human body model, MIL STD 833D method 3015.7, all pins except OUT_IFA pin OUT_IFA Max 7.0 VCC+0.3 10 +125 Unit V V dBm C -500 -500 +500 +250 V V Normal Operating Conditions Parameter Supply voltage Operating temperature Input frequency Frequency deviation FSK data rate FM bandwidth ASK data rate Symbol Vcc Ta fi f RFSK fm RASK Condition Min 2.5 -40 300 5 Max 5.5 +85 450 120 40 15 80 Unit V C MHz kHz kbit/s kHz kbit/s at FM or FSK NRZ NRZ TH71102 Data Sheet 3901071102 Page 8 of 20 Nov. 2001 Rev. 005 TH71102 315/433MHz FSK/FM/ASK Receiver DC Characteristics all parameters under normal operating conditions, unless otherwise stated; typical values at Ta = 23 C and Vcc = 3 V Parameter Standby current Total supply current at low gain Total supply current at high gain Opamp input offset voltage Opamp input offset current Opamp input bias current RSSI voltage at low input level RSSI voltage at high input level Symbol ISBY Icc, low Icc, high Voffs Ioffs Ibias VRSSI, low VRSSI, high Condition ENRX=0 ENRX=1, LNA at LOW GAIN ENRX=1, LNA at HIGH GAIN IOAP - IOAN 0.5 * (IOAP + IOAN) Pi = -65 dBm, LNA at LOW GAIN Pi = -35 dBm, LNA at LOW GAIN Min 5.0 6.5 -20 -50 -100 0.5 1.25 Typ 6.5 8.2 Max 100 8.0 10.0 20 50 100 1.5 2.45 Unit nA mA mA mV nA nA V V 1.0 1.9 AC System Characteristics all parameters under normal operating conditions, unless otherwise stated; all parameters based on test circuits for FSK (Fig. 2), FM (Fig. 4) and ASK (Fig. 5), respectively; typical values at Ta = 23 C and Vcc = 3 V, RF at 433.6 MHz, second IF at 10.7 MHz Parameter start-up time - FSK/FM start-up time - ASK Symbol TFSK TASK Condition ENRX from 0 to 1, valid data at output depends on ASK detector time constant, valid data at output BIF2 = 40kHz f = 15kHz (FSK/FM) -3 BER 310 BIF2 = 150kHz f = 50kHz (FSK/FM) -3 BER 310 BIF2 = 40kHz -3 BER 310 BIF2 = 150kHz -3 BER 310 -3 BER 310 LNA at LOW GAIN -3 BER 310 LNA at LOW GAIN Min Typ Max 0.9 R3*C12 + TFSK -111 Unit ms ms input sensitivity - FSK (narrow band) input sensitivity - FSK (wide band) Pmin, n dBm Pmin, w -104 dBm input sensitivity - ASK PminA, n (narrow band) input sensitivity - ASK PminA, w (wide band) maximum input signal - FSK/FM Pmax, FM maximum input signal - ASK spurious emission image rejection blocking immunity VCO gain Charge pump current Pmax, ASK Pspur Pimag Pblock KVCO ICP -109 -106 0 -10 -70 dBm dBm dBm dBm dBm dB dB MHz/V A fblock > 2MHz, note 1 65 57 250 60 Notes: 1. desired signal with FSK/FM or ASK modulation, CW blocking signal TH71102 Data Sheet 3901071102 Page 9 of 20 Nov. 2001 Rev. 005 TH71102 315/433MHz FSK/FM/ASK Receiver Test Circuits FSK Reception C14 C15 C16 VCC VCC CP C13 RSSI OUTN OUTP OAP OAN VEE VEE OUT_OA XTAL IN_DEM C12 VCC C1 RO OUT_IFA VCC FBC2 CERRES VCC VCC ENRX C11 R1 C3 LF VEE GAIN_LNA OUT_LNA IN_LNA FBC1 C9 LQFP32 IN_MIX1 C10 IN_IFA VEE IF1N IF1P L2 SAWFIL VCC VEE VEE VCC C5 VCC CERFIL OUT_MIX2 C7 L3 C8 LCFIL L1 C4 C6 L4 L5 CB* VCC Fig. 2: Test circuit for FSK reception TH71102 Data Sheet 3901071102 Page 10 of 20 Nov. 2001 Rev. 005 TH71102 315/433MHz FSK/FM/ASK Receiver FSK test circuit component list to Fig. 2 Part C1 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 CP C14 C15 C16 R1 L1 L2 L3 L4 L5 XTAL Size 0805 0805 0603 0603 0603 0603 0603 0805 0603 0603 0603 0603 0805 0805 0805 0603 0805 0603 0603 0603 0805 0805 HC49 SMD QCC8C Value / Type 15 pF 1 nF 3.3 pF 3.3 pF 4.7 pf 2.2 pf 27 pF 33 nF 1 nF 1 nF 1.5 pF 680 pF 10 - 12 pF 10 - 47 pF 10 - 47 pF 330 pF 10 k 33 nH 33 nH 15 nH 100 nH 100 nH 23.49444 MHz @ RF = 433.6 MHz B3555 @ RF = 433.6 MHz Tolerance 10% 10% 5% 5% 5% 5% 5% 10% 10% 10% 5% 10% 5% 5% 5% 10% 10% 5% 5% 5% 5% 5% 25ppm calibration 30ppm temp. Description crystal series capacitor loop filter capacitor capacitor to match to SAW filter input capacitor to match to SAW filter output LNA output tank capacitor MIX1 input matching capacitor IF1 tank capacitor IFA feedback capacitor IFA feedback capacitor IFA feedback capacitor DEMOD phase-shift capacitor DEMOD coupling capacitor CERRES parallel capacitor demodulator output low-pass capacitor, depending on data rate demodulator output low-pass capacitor, depending on data rate RSSI output low-pass capacitor loop filter resistor inductor to match SAW filter inductor to match SAW filter LNA output tank inductor IF1 tank inductor IF1 tank inductor fundamental-mode crystal, Cload = 10 pF to 15pF, C0, max = 7 pF, Rm, max = 50 SAWFIL B3dB = 860 kHz low-loss SAW filter from EPCOS 100 kHz (f0 = 433.92 MHz) TBD 40 kHz CERFIL leaded type SMD type SFE10.7MFP @ BIF2 = 40 kHz SFECV10.7MJS-A @ BIF2 = 150 kHz CDACV10.7MG18-A ceramic filter from Murata CERRES SMD type ceramic demodulator tank from Murata NIP - not in place, may be used optionally TH71102 Data Sheet 3901071102 Page 11 of 20 Nov. 2001 Rev. 005 TH71102 315/433MHz FSK/FM/ASK Receiver FSK Circuit with AFC and Ceramic Resonator Tolerance Compensation C14 C15 R4 R5 C16 C17 C18 VCC R3 VCC CP C13 VD OUTN RSSI VEE OUTP OAP OAN VEE XTAL C1 RO VCC OUT_OA IN_DEM OUT_IFA VCC FBC2 C9 FBC1 C12 VCC CERRES VCC ENRX C11 R1 C3 LF VEE GAIN_LNA OUT_LNA IN_LNA L2 SAWFIL VEE C5 VCC LQFP32 IN_MIX1 C10 IN_IFA VEE IF1N IF1P VCC VEE VCC CERFIL OUT_MIX2 C7 C8 LCFIL L1 C4 L3 C6 L4 L5 CB* VCC Fig. 3: Test circuit for FSK with AFC and resonator compensation Circuit Feature ! ! ! ! Improves input frequency acceptance range up to RFnom 50 kHz Eliminates calibration tolerances of ceramic resonator Eliminates temperature tolerances of ceramic resonator Non-inverted and inverted CMOS-compatible outputs TH71102 Data Sheet 3901071102 Page 12 of 20 Nov. 2001 Rev. 005 TH71102 315/433MHz FSK/FM/ASK Receiver FSK test circuit with AFC component list to Fig. 3 Part C1 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 CP C14 C15 C16 C17 C18 0805 Size 0805 0805 0603 0603 0603 0603 0603 0805 0603 0603 0603 0603 0805 0805 0805 0603 Value / Type 15 pF 1 nF 3.3 pF 3.3 pF 4.7 pF 2.2 pF 27 pF 33 nF 1 nF 1 nF 1.5 pF 680 pF 27 pF 10 - 47 pF 10 - 47 pF 330 pF 33 nF 33 nF 10 nF 1 nF 10 k 100 k 680 k 680 k 33 nH 33 nH 15 nH 100 nH 100 nH BB535 23.49444 MHz @ RF = 433.6 MHz B3555 @ RF = 433.6 MHz SFE10.7MFP @ BIF2 = 40 kHz SFECV10.7MJS-A @ BIF2 = 150 kHz CDACV10.7MG18-A Tolerance 10% 10% 5% 5% 5% 5% 5% 10% 10% 10% 5% 10% 5% 5% 5% 10% 10% 10% Description crystal series capacitor loop filter capacitor capacitor to match to SAW filter input capacitor to match to SAW filter output LNA output tank capacitor MIX1 input matching capacitor IF1 tank capacitor IFA feedback capacitor IFA feedback capacitor IFA feedback capacitor DEMOD phase-shift capacitor DEMOD coupling capacitor ceramic resonator loading capacitor demodulator output low-pass capacitor, depending on data rate demodulator output low-pass capacitor, depending on data rate RSSI output low-pass capacitor integrator capacitor, fixed integrator capacitor, @ 0.5 to 2 kbit/s NRZ integrator capacitor, @ 2 to 20 kbit/s NRZ integrator capacitor, @ 20 to 40 kbit/s NRZ loop filter resistor varactor diode biasing resistor integrator resistor integrator resistor inductor to match SAW filter inductor to match SAW filter LNA output tank inductor IF1 tank inductor IF1 tank inductor varactor diode from Infineon fundamental-mode crystal, Cload = 10 pF to 15pF, C0, max = 7 pF, Rm, max = 50 R1 R3 R4 R5 L1 L2 L3 L4 L5 VD XTAL 0805 0805 0805 0805 0603 0603 0603 0805 0805 SOD-323 HC49 SMD QCC8C 10% 10% 10% 10% 5% 5% 5% 5% 5% SAWFIL CERFIL leaded type SMD type 25ppm calibration 30ppm temp. B3dB = 860 kHz low-loss SAW filter from EPCOS 100 kHz (f0 = 433.92 MHz) TBD ceramic filter from Murata 40 kHz CERRES SMD type ceramic demodulator tank from Murata NIP - not in place, may be used optionally TH71102 Data Sheet 3901071102 Page 13 of 20 Nov. 2001 Rev. 005 TH71102 315/433MHz FSK/FM/ASK Receiver FM Reception R6 C14 R5 C16 C15 R4 R3 VCC VCC CP C13 OUTN RSSI VEE OUTP OAP OAN VEE OUT_OA XTAL IN_DEM C12 VCC C1 RO OUT_IFA VCC FBC2 CERRES VCC VCC ENRX C11 R1 C3 LF VEE GAIN_LNA OUT_LNA IN_LNA VEE FBC1 C9 LQFP32 IN_MIX1 C10 IN_IFA VEE IF1N IF1P L2 SAWFIL VCC VEE VCC C5 VCC CERFIL OUT_MIX2 C7 C8 LCFIL L1 C4 L3 C6 L4 L5 CB* VCC Fig. 4: Test circuit for FM reception TH71102 Data Sheet 3901071102 Page 14 of 20 Nov. 2001 Rev. 005 TH71102 315/433MHz FSK/FM/ASK Receiver FM test circuit component list to Fig. 4 Part C1 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 CP C14 C15 C16 R1 R3 R4 R5 R6 L1 L2 L3 L4 L5 XTAL Size 0805 0805 0603 0603 0603 0603 0603 0805 0603 0603 0603 0603 0805 0805 0805 0603 0805 0805 0805 0805 0805 0603 0603 0603 0603 0603 HC49 SMD QCC8C Value / Type 15 pF 1 nF 3.3 pF 3.3 pF 4.7 pF 2.2 pF 27 pF 33 nF 1 nF 1 nF 1.5 pF 680 pF 10 - 12 pF 100 pF 100 pF 330 pF 10 k 12 k 6.8 k 33 k 33 k 33 nH 33 nH 15 nH 100 nH 100 nH 23.49444 MHz @ RF = 433.6 MHz B3555 @ RF = 433.6 MHz SFE10.7MFP @ BIF2 = 40 kHz SFECV10.7MJS-A @ BIF2 = 150 kHz CDACV10.7MG18-A Tolerance 10% 10% 5% 5% 5% 5% 5% 10% 10% 10% 5% 10% 5% 5% 5% 10% 10% 5% 5% 5% 5% 5% 5% 5% 5% 5% Description crystal series capacitor loop filter capacitor capacitor to match to SAW filter input capacitor to match to SAW filter output LNA output tank capacitor MIX1 input matching capacitor IF1 tank capacitor IFA feedback capacitor IFA feedback capacitor IFA feedback capacitor DEMOD phase-shift capacitor DEMOD coupling capacitor CERRES parallel capacitor sallen-Key low-pass filter capacitor, to set cut-off frequency sallen-Key low-pass filter capacitor, to set cut-off frequency RSSI output low-pass capacitor loop filter resistor sallen-Key filter resistor, to set desired filter characteristic sallen-Key filter resistor, to set desired filter characteristic sallen-Key filter resistor, to set cut-off frequency sallen-Key filter resistor, to set cut-off frequency inductor to match SAW filter inductor to match SAW filter LNA output tank inductor IF1 tank inductor IF1 tank inductor fundamental-mode crystal, Cload = 10 pF to 15pF, C0, max = 7 pF, Rm, max = 50 SAWFIL CERFIL leaded type SMD type 25ppm calibration 30ppm temp. B3dB = 860 kHz low-loss SAW filter from EPCOS 100 kHz (f0 = 433.92 MHz) TBD ceramic filter from Murata 40 kHz CERRES SMD type ceramic demodulator tank from Murata NIP - not in place, may be used optionally TH71102 Data Sheet 3901071102 Page 15 of 20 Nov. 2001 Rev. 005 TH71102 315/433MHz FSK/FM/ASK Receiver ASK Reception R3 C13 C12 VCC RSSI OUTN OUTP OAP OAN VEE VEE OUT_OA XTAL RO IN_DEM OUT_IFA VCC FBC2 VCC C1 VCC VCC ENRX VCC C11 R1 C3 LF VEE GAIN_LNA OUT_LNA IN_LNA FBC1 C9 LQFP32 IN_MIX1 C10 IN_IFA VEE IF1N IF1P L2 SAWFIL VCC VEE VEE VCC C5 VCC CERFIL OUT_MIX2 C7 L3 C6 C8 LCFIL L1 C4 L4 L5 CB* VCC Fig. 5: Test circuit for ASK reception TH71102 Data Sheet 3901071102 Page 16 of 20 Nov. 2001 Rev. 005 TH71102 315/433MHz FSK/FM/ASK Receiver ASK test circuit component list to Fig. 5 Part C1 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 R1 R3 L1 L2 L3 L4 L5 XTAL Size 0805 0805 0603 0603 0603 0603 0805 0805 0603 0603 0805 0603 0805 0603 0603 0603 0603 0603 0603 HC49 SMD QCC8C Value / Type 15 pF 1 nF 3.3 pF 3.3 pF 4.7 pF 2.2 pF 27 pF 33 nF 1 nF 1 nF 1 nF to 10 nF 330 pF 10 k 100 k 33 nH 33 nH 15 nH 100 nH 100 nH 23.49444 MHz @ RF = 433.6 MHz B3555 @ RF = 433.6 MHz SFE10.7MFP @ BIF2 = 40 kHz SFECV10.7MJS-A @ BIF2 = 150 kHz Tolerance 10% 10% 5% 5% 5% 5% 5% 10% 10% 10% 10% 10% 10% 5% 5% 5% 5% 5% 5% Description crystal series capacitor loop filter capacitor capacitor to match to SAW filter input capacitor to match to SAW filter output LNA output tank capacitor MIX1 input matching capacitor IF1 tank capacitor IFA feedback capacitor IFA feedback capacitor IFA feedback capacitor ASK data slicer capacitor, depending on data rate RSSI output low-pass capacitor loop filter resistor ASK data slicer resistor, depending on data rate inductor to match SAW filter inductor to match SAW filter LNA output tank inductor IF1 tank inductor IF1 tank inductor fundamental-mode crystal, Cload = 10 pF to 15pF, C0, max = 7 pF, Rm, max = 50 SAWFIL CERFIL leaded type SMD type 25ppm calibration 30ppm temp. B3dB = 860 kHz low-loss SAW filter from EPCOS 100 kHz (f0 = 433.92 MHz) TBD ceramic filter from Murata 40 kHz NIP - not in place, may be used optionally TH71102 Data Sheet 3901071102 Page 17 of 20 Nov. 2001 Rev. 005 TH71102 315/433MHz FSK/FM/ASK Receiver Package Dimensions D D1 24 17 25 16 b e E E1 32 9 1 8 A A2 A1 L Fig. 6: LQFP32 (Low Quad Flat Package) All Dimension in mm, coplanarity < 0.1mm E1, D1 A A1 A2 e b min 0.05 1.35 0.30 7.00 0.8 max 1.60 0.15 1.45 0.45 All Dimension in inch, coplanarity < 0.004" min 0.002 0.053 0.012 0.276 0.031 max 0.630 0.006 0.057 0.018 L 0.45 0.75 0.018 E, D 9.00 0 7 0 0.354 0.030 7 TH71102 Data Sheet 3901071102 Page 18 of 20 Nov. 2001 Rev. 005 TH71102 315/433MHz FSK/FM/ASK Receiver Your Notes TH71102 Data Sheet 3901071102 Page 19 of 20 Nov. 2001 Rev. 005 TH71102 315/433MHz FSK/FM/ASK Receiver Your Notes Important Notice Devices sold by Melexis are covered by the warranty and patent indemnification provisions appearing in its Term of Sale. Melexis makes no warranty, express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the described devices from patent infringement. Melexis reserves the right to change specifications and prices at any time and without notice. Therefore, prior to designing this product into a system, it is necessary to check with Melexis for current information. This product is intended for use in normal commercial applications. Applications requiring extended temperature range, unusual environmental requirements, or high reliability applications, such as military, medical life-support or life-sustaining equipment are specifically not recommended without additional processing by Melexis for each application. The information furnished by Melexis is believed to be correct and accurate. However, Melexis shall not be liable to recipient or any third party for any damages, including but not limited to personal injury, property damage, loss of profits, loss of use, interrupt of business or indirect, special incidental or consequential damages, of any kind, in connection with or arising out of the furnishing, performance or use of the technical data herein. No obligation or liability to recipient or any third party shall arise or flow out of Melexis' rendering of technical or other services. (c) 2000 Melexis GmbH. All rights reserved. For the latest version of this document. Go to our website at www.melexis.com Or for additional information contact Melexis Direct: Europe and Japan: Phone: +32 1361 1631 E-mail: sales_europe@melexis.com All other locations: Phone: +1 603 223 2362 E-mail: sales_usa@melexis.com QS9000, VDA6.1 and ISO14001 Certified TH71102 Data Sheet 3901071102 Page 20 of 20 Nov. 2001 Rev. 005 |
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